文件名称：Art of Writing TestBenches
文件大小：410KB
文件格式：PDF
更新时间：2016-06-09 11:44:32
TestBenches
Writing testbench is as complex as writing the RTL code itself. This days ASIC's are getting more and more complex and thus the challenge to verify this complex ASIC. Typically 60-70% of time in any ASIC is spent on verification/validation/testing. Even though above facts are well know to most of the ASIC engineers, but still engineers think that there is no glory in verification. I have picked up few examples from the VLSI classes that I used to teach during 1999-2001, when I was in Chennai. Please feel free to give your feedback on how to improve below tutorial.