文件名称：Art of Writing Testbenches
文件大小：97KB
文件格式：PDF
更新时间：2012-12-31 14:55:55
FPGA 数字电路设计 ASIC测试
数字电路设计经典！ Writing testbench is as complex as writing the RTL code itself. This days ASIC's are getting more and more complex and thus the challenge to verify this complex ASIC. Typically 60-70% of time in any ASIC is spent on verification/validation/testing. Even though above facts are well know to most of the ASIC engineers, but still engineers think that there is no glory in verification.