I'm trying to write a Verilog module that multiplies two 4bit inputs, without using * operator, but I get some errors:
我正在尝试编写一个Verilog模块，它可以在不使用*操作符的情况下，将两个4位的输入相乘，但是我得到了一些错误:
module multiplier(
output[7:0] prod,
input[3:0] a,
input[3:0] b);
reg [7:0] result=8'h00;
always @(*)
begin
for(i=0;i<4;i=i+1)
begin
if((b&(1<<<i))!=0)
begin
result = result+(a<<<i);
end
end
end
assign prod = result;
endmodule
Errors:
错误:
[Synth 8-2715] syntax error near =
[Synth 8-2715]语法错误接近=。
[Synth 8-2715] syntax error near =
[Synth 8-2715]语法错误接近=。
[Synth 8-993] result is an unknown type
[Synth 8-993]结果是一种未知类型。
[Common 17-69] Command failed: Vivado Synthesis failed
[普通的17-69]命令失败:Vivado综合失败。
What am I doing wrong?
我做错了什么?
EDIT: I modified the code, now i get: [Synth 8-1031] i is not declared
编辑:我修改了代码，现在我得到:[Synth 8-1031]我没有声明。
2 个解决方案
#1
1
reg [7:0] result=16'h00;
Should be
应该是
reg [7:0] result=8'h00;
#2
0
module multiplier(
output[7:0] prod,
input[3:0] a,
input[3:0] b);
reg [7:0] result;
reg[2:0] i;
always @(*)
begin
result=0;
for(i=0;i<4;i=i+1)
begin
if(b[i]==1'b1)
begin
result = result+(a<<i);
end
end
end
assign prod = result;
endmodule
For your code, if I had a = 15 and b = 15, the result would have been 72. You must assign a value for result in always block result=0;
对于你的代码，如果我有a = 15和b = 15，结果应该是72。你必须为结果指定一个值，结果总是block result=0;
#1
1
reg [7:0] result=16'h00;
Should be
应该是
reg [7:0] result=8'h00;
#2
0
module multiplier(
output[7:0] prod,
input[3:0] a,
input[3:0] b);
reg [7:0] result;
reg[2:0] i;
always @(*)
begin
result=0;
for(i=0;i<4;i=i+1)
begin
if(b[i]==1'b1)
begin
result = result+(a<<i);
end
end
end
assign prod = result;
endmodule
For your code, if I had a = 15 and b = 15, the result would have been 72. You must assign a value for result in always block result=0;
对于你的代码，如果我有a = 15和b = 15，结果应该是72。你必须为结果指定一个值，结果总是block result=0;