文件名称：Binding System Verilog Module to VHDL design
文件大小：2.33MB
文件格式：PDF
更新时间：2013-06-28 13:15:58
System Verilog VHDL
Binding System Verilog Module to VHDL design. A pretty good article guiding you how to bind system verilog module to VHDL design. Especially useful in mixed signal model.