文件名称：myhdl-python-fpga.pdf
文件大小：629KB
文件格式：PDF
更新时间：2023-04-18 08:29:01
myHDL Python FPG
The goal of the MyHDL project is to empower hardware designers with the elegance and simplicity of the Python language. MyHDL is a free, open-source package for using Python as a hardware description and verification language. Python is a very high level language, and hardware designers can use its full power to model and simulate their designs. Moreover, MyHDL can convert a design to Verilog or VHDL. This provides a path into a traditional design flow.