文件名称：VHDL 4选一选择器
文件大小：10KB
文件格式：DOC
更新时间：2015-04-14 08:40:43
选择器
VHDL语言，四选一选择器试验。 entity mux41a is port(a,b:in std_logic; s1,s2,s3,s4:in std_logic; y: out std_logic); end entity mux41a; architecture one of mux41a is signal ab:std_logic_vector(1 downto 0); begin ab <= a&b; process(ab,s1,s2,s3,s4) begin case ab is when "00" => y<=s1; when "01" => y<=s2; when "10" => y<=s3; when "11" => y<=s4; when others => null; end case; end process; end architecture one;