【文件属性】：
文件名称：Altera的Verilog代码编码规范
文件大小：2.04MB
文件格式：PDF
更新时间：2016-05-27 15:25:47
FPGA
Altera的Verilog代码编码规范
Logic Function Precision and Reliability
Design for Rapid Simulation
Best Trade-off between Circuit Size and
Performance
Good Readability and Migration
Good Reusability