文件名称：基于 FPGA 的 I2C 总线模拟，采用 Verilog HDL 语言编写
文件大小：241KB
文件格式：ZIP
更新时间：2023-05-29 06:21:46
FPGA Verilog I2C
基于FPGA的I2C总线模拟，采用Verilog HDL语言编写 (FPGA-based I2C bus simulation, using Verilog HDL.)
【文件预览】：
xst
----work()
--------hdllib.ref(231B)
--------vlg5C()
--------vlg07()
--------vlg67()
prjname.lso
i2c_master_top.v
i2c_slave_model.udo
coregen.log
__projnav.log
i2c_master_bit_ctrl.v
I2C.dhp
i2c_master_bit_ctrl.stx
timescale.v
wb_master_model.v.bak
i2c_master_byte_ctrl.ngr
i2c_slave_model.v
i2c_master_bit_ctrl.syr
work
----i2c_slave_model()
--------verilog.asm(35KB)
--------_primary.vhd(492B)
--------_primary.dat(4KB)
----_info(322B)
----glbl()
--------verilog.asm(4KB)
--------_primary.vhd(172B)
--------_primary.dat(528B)
i2c_master_bit_ctrl.v.bak
i2c_master_byte_ctrl.v.bak
i2c_master_top.stx
transcript
i2c_master_bit_ctrl.prj
i2c_master_bit_ctrl.lso
i2c_master_bit_ctrl.cmd_log
i2c_master_byte_ctrl.syr
coregen.prj
i2c_slave_model.fdo
i2c_master_top.lso
automake.log
wb_master_model.v
i2c_master_byte_ctrl.stx
i2c_master_top.cmd_log
i2c_master_byte_ctrl.v
i2c_master_top.v.bak
i2c_slave_model.ndo
i2c_master_defines.v.bak
i2c_master_defines.v
i2c_master_top.syr
i2c_master_byte_ctrl.ngc
I2C.npl
i2c_master_top.ngc
i2c_master_bit_ctrl.ngr
__projnav
----runXst_tcl.rsp(91B)
----i2c_master_byte_ctrl.xst(1020B)
----xst_sprjTOstx_tcl.rsp(72B)
----coregen.rsp(111B)
----I2C_flowplus.gfl(805B)
----I2C.gfl(2KB)
----i2c_master_bit_ctrl.xst(1016B)
----i2c_master_top.xst(996B)
i2c_master_top.ngr
i2c_master_top.prj
tst_bench_top.v
i2c_slave_model.v.bak
i2c_master_byte_ctrl_vhdl.prj
i2c_master_byte_ctrl.cmd_log
i2c_master_byte_ctrl.lso
i2c_master_bit_ctrl_vhdl.prj
i2c_master_bit_ctrl.ngc
i2c_master_top_vhdl.prj
i2c_master_byte_ctrl.prj