【文件属性】:
文件名称:计数器vhdl
文件大小:27KB
文件格式:DOC
更新时间:2017-05-07 09:35:40
计数器vhdl
6进制计数器的vhdl描述
entity frequencies is
port(clk:in std_logic;
q:out std_logic);
end frequencies;
architecture behav of frequencies is
signal time:integer range 0 to 5;
begin
end behav;