Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog

【文件属性】：

文件名称：Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog

文件大小：556KB

文件格式：PDF

更新时间：2016-04-30 09:56:56

cdc

IEEE paper: Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog