文件名称：四位二进制计数器译码程序
文件大小：18KB
文件格式：DOC
更新时间：2013-07-10 16:20:03
四位二进制计数器译码程序
library IEEE; use IEEE.std_logic_1164.all; entity sysegd is port (x : in std_logic_vector(3 downto 0); s : out std_logic_vector (6 downto 0)); end entity; architecture bin27seg_arch of sysegd is begin process(x) begin case x(3 downto 0) is when "0000" => s <= "1111110"; -- 0 when "0001" => s <= "0110000"; -- 1 when "0010" => s <= "1101101"; -- 2 when "0011" => s <= "1111001"; -- 3 when "0100" => s <= "0110011"; -- 4 when "0101" => s <= "1011011"; -- 5 when "0110" => s <= "1011111"; -- 6 when "0111" => s <= "1110000"; -- 7 when "1000" => s <= "1111111"; -- 8 when "1001" => s <= "1111011"; -- 9 when "1010" => s <= "1110111"; -- A when "1011" => s <= "0011111"; -- b when "1100" => s <= "1001110"; -- c when "1101" => s <= "0111101"; -- d when "1110" => s <= "1001111"; -- E when "1111" => s <= "1000111"; -- F when others => NULL; end case; end process; end architecture;