module tw(clk,k_or,k1,k2);
input clk;
output k_or,k1,k2;
reg [2:0] c1,c2;
reg m1,m2;
initial
begin
c1=0;
c2=0;
m1=0;
m2=0;
end
always @(posedge clk)
begin
if(c1==a) c1<=0;else c1<=c1+1;
if(c1==1) m1=~m1;else if(c1==b) m1=~m1;end
always @(negedge clk)
begin
if(c2==a) c2<=0;else c2<=c2+1;
if(c2==1) m2=~m2;else if(c2==b) m2=~m2;end
assign k1=m1;
assign k2=m2;
assign k_or=m1|m2;
endmodule
分频系数，则采用如下公式
a=n-1;
b=n-2;
n为分频系数。