文件名称：UART参考设计 Xilinx提供VHDL代码
文件大小：11KB
文件格式：ZIP
更新时间：2013-02-03 02:23:01
VHDL UART xilinx
This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
【文件预览】：
rcvr_tb.vhd
txmit.vhd
txmit_tb.vhd
readme.doc
readme.txt
rcvr.vhd
uart.vhd