文件名称：多功能数字钟 EDA
文件大小：41KB
文件格式：DOC
更新时间：2013-06-30 07:55:34
数字钟
4位数字频率计控制模块 module fre_ctrl(clk,rst,count_en,count_clr,load); input clk,rst; output count_en,count_clr,load; reg count_en,load; always @(posedge clk) begin if(rst) begin count_en<=0; load<=1; end else begin count_en<=~count_en; load<=~count_en; //load信号的产生 end end assign count_clr=~clk&load; //count_clr信号的产生 endmodule