【文件属性】:
文件名称:verilog-------时钟设计
文件大小:2KB
文件格式:BAK
更新时间:2018-08-28 03:45:50
FPGA
FPGA 综合实验
always @(posedge clock0 or posedge clr)
begin
if (clr == 1)
begin
clk_temp <= 0;
clock1<= 0;
end
else
begin
clk_temp <= clk_temp + 1;
if (clk_temp == 7'b1111111)
clock1 <= clock1+1;
else
clock1 <= clock1;
end