文件名称：Digital-electronics-1
文件大小：1.61MB
文件格式：ZIP
更新时间：2024-03-05 14:38:42
Digital-electronics-1 实验室 源代码 begin writeline ( " Boris voní " ); end ; 摩根法律模拟 architecture dataflow of gates is begin f_o <= (( not b_i) and a_i) or (( not c_i) and ( not b_i)); fnand_o <= not ( not (( not b_i) and a_i) and not (( not c_i) and ( not b_i))); fnor_o <= not (b_i or ( not a_i)) or not (c_i or b_i); end architecture dataflow ;
【文件预览】：
Digital-electronics-1-main
----Docs()
--------VHDL_guide.pdf(476KB)
--------Xilinx.lic(943B)
--------nexys-a7-sch.pdf(740KB)
--------vhdl_cheatsheet.pdf(190KB)
--------git_cheatsheet.pdf(98KB)
--------ds180_7Series_Overview.pdf(446KB)
----Labs()
--------01-gates()
----LICENSE(1KB)
----README.md(404B)