文件名称：Verilog HDL 入门实例（含 ADC、FIFO、ADDER、MULTIPLIER等）
文件大小：187KB
文件格式：ZIP
更新时间：2023-05-29 06:12:37
Verilog HDL 入门 实例
Verilog HDL 入门实例（含 ADC、FIFO、ADDER、MULTIPLIER等） (many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.)
【文件预览】：
dds.v.txt
cla_8bits.v
SYNTHPIC.ZIP
multi_select_1.v
COMPARE.V
half_adder_2.v
half_adder_3.v
myrand.c.txt
nco.v.txt
MUL16.V
gencrc.v.txt
decoder3x8.v
FIFO.V
ADC_16bit.v
lead_8bits_adder2.v
ALL.V
binarytogray.v
PLI.TAR
pic.v.txt
FIFO_2.V
DECODER1.V
string.v.txt
half_adder_1.v
encoder8x3_2.v
fifo.v.txt
RISC8.ZIP
TEST.V
adder_8bit.v
wpulse.v.txt
div16.v.txt
MUX8X8.V
mult_select.v
full_adder_2.v
lead_8bits_adder.v
full_adder_1.v
framer.v.txt
mult16.v.txt
frequency5x2.v
encoder8x3.v
SHIFTER.V
test_cla_8bits.v
adder_8bit_2.v
fifo_16x16.v
mult_piped_8x8.v
testing.v.txt
sequence_dectect.v
onehot.v.txt