文件名称：Design of a complex divider
文件大小：158KB
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更新时间：2016-12-04 13:00:28
复数除法器 verilog 流水线
We describe a hardware-oriented design of a complex division algorithm proposed in .6 This algorithm is similar to a radix-r digit-recurrence division algorithm with real operands and prescaling. Prescaling of complex operands allows efficient selection of complex quotient digits in higher radix. The use of the digit-recurrence method allows hardware implementation similar to that of conventional dividers. Moreover, this method makes correct rounding of complex quotient possible. On the other hand, the proposed scheme requires the use of prescaling tables which are more demanding than tables in similar dividers with real operands. In this paper we present main design ideas, implementation details, and give a rough estimate of the expected latency. We also make a comparison with the estimated latency of the Smith’s algorithm used in software routines for complex division.