文件名称：SYSTEMVERILOG FOR VERIFICATION
文件大小：3.1MB
文件格式：PDF
更新时间：2014-06-13 23:53:55
SYSTEMVERILOG FOR VERIFICATION
This book is the first one you should read to learn the SystemVerilog verification language constructs. It describes how the language works and includes many examples on how to build a basic coverage-driven, constrained-random layered testbench using Object-Oriented Programming (OOP). The book has many guidelines on building testbenches, which help show why you want to use classes, randomization, and functional coverage. Once you have learned the language, pick up some of the methodology books listed in the References section for more information on building a testbench.