文件名称：UART verilog代码
文件大小：86KB
文件格式：RAR
更新时间：2020-11-30 07:59:38
UART RTL
The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with modem or other external devices, like another computer using a serial cable and RS232 protocol. This core is designed to be maximally compatible with the industry standard National Semiconductors’ 16550A device.
【文件预览】：
uart16550
----fv()
--------.keepme(0B)
----assertions()
--------rx_fifo_vunit.psl(2KB)
--------tx_fifo_vunit.psl(2KB)
--------transmitter_vunit.psl(3KB)
--------receiver_vunit.psl(6KB)
----rtl()
--------uart_receiver.v(17KB)
--------uart_tfifo.v(9KB)
--------uart_defines.v(10KB)
--------timescale.v(4KB)
--------uart_rfifo.v(11KB)
--------uart_wb.v(11KB)
--------uart_regs.v(28KB)
--------uart_sync_flops.v(6KB)
--------uart_transmitter.v(12KB)
--------uart_top.v(11KB)
--------uart_debug_if.v(6KB)
--------raminfr.v(6KB)
----lint()
--------log()
--------bin()
--------out()
--------run()
----sim()
--------rtl_sim()
--------gate_sim()
----doc()
----bench()
--------vhdl()
--------verilog()
----syn()
--------log()
--------bin()
--------src()
--------out()
--------run()