文件名称：Utilizing clock-gating efficiency to reduce power
文件大小：184KB
文件格式：PDF
更新时间：2015-11-02 16:28:50
clock gating, power
As consumers continue to demand more functionality in smaller, more energy efficient devices, power optimization rules a hardware designer’s life. It typically takes multiple iterations over weeks of optimization to achieve power goals and budgets. While power should be optimized at all stages of the design flow, many times it is only addressed after initial register transfer level (RTL) synthesis runs uncover inefficiencies.