文件名称：Gcc连接动态库
文件大小：32KB
文件格式：PDF
更新时间：2021-05-11 04:41:48
连接动态库
Communication between cores in mainstream multi-core machines is enabled by a shared memory. To send information from one core to another, one core writes to mem- ory and the other reads from memory. Unfortunately, memory is extremely slow when compared with computation. Processor designers go to great lengths to reduce the la- tency of memory by introducing caches and buffers in the memory system. In the design of such a memory, there is a fundamental choice: one can design intricate protocols that hide the details, preserving the illusion of a simple memory interface while introducing communication delay, or one can allow memory accesses to appear to happen out of order, betraying some of the internal workings of the machine. Mainstream processor vendors all opt for the latter: ARM, IBM’s Power, SPARC-TSO, and Intel’s x86 and Itanium architectures allow the programmer to see strange behaviour at the interface to memory in order to allow agressive optimisation in the memory subsystem.