文件名称：Reconfigurable design and implementation of the MD6 Hash function (2010年)
文件大小：247KB
文件格式：PDF
更新时间：2024-06-05 00:06:45
工程技术 论文
Efficient reconfigurable field programmable gate array (FPGA) architectures for the MD6-224/256/384/512 Hash algorithm are proposed in this article. The basic iterative compact design requires 923 ALMs and achieves a throughput ranging from 225 Mbit/s to