文件名称：An ASIC Design for a High Speed Implementation of the Hash Function SHA-256
文件大小：225KB
文件格式：PDF
更新时间：2020-12-22 15:26:11
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An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a re- duction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13μm technology.