ti am335x datasheet

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文件名称：ti am335x datasheet
文件大小：17.23MB
文件格式：PDF
更新时间：2017-07-13 04:05:53
The Microprocessor Unit (MPU) subsystem of the device handles transactions between the ARM core (ARM® CortexTM-A8 Processor), the L3 interconnect, and the interrupt controller (INTC). The MPU subsystem is a hard macro that integrates the ARM® CortexTM-A8 Processor with additional logic for protocol conversion, emulation, interrupt handling, and debug enhancements. CortexTM-A8 is an ARMv7 compatible, dual-issue, in-order execution engine with integrated L1 and L2 caches with NEONTM SIMD Media Processing Unit. An Interrupt Controller is included in the MPU subsystem to handle host interrupt requests in the system. The MPU subsystem includes CoreSight compliant logic to allow the Debug Sub-system access to the CortexA8 debug and emulation resources, including the Embedded Trace Macrocell. The MPU subsystem has three functional clock domains, including a high-frequency clock domain used by the CortexTM-A8. The high-frequency domain is isolated from the rest of the system by asynchronous bridges.