文件名称：Cell-based IC Design and Verification
文件大小：5.83MB
文件格式：PDF
更新时间：2012-11-19 04:50:58
ASIC Design and Verification
1.Design Flow Overview 2.Verilog at a Glance 3.RTL Simulation 4.Code Coverage Analysis 5.RTL Synthesis 6.Logic Synthesis 7.Gate-level Delay Calculation 8.Static Timing Analysis 9.Power Analysis & Optimization 10.DFT & ATPG 11.Automatic Physical Design 12.Physical Verification 13.Formal Equivalence Checking