文件名称：静态时序分析详解.zip
文件大小：2.89MB
文件格式：ZIP
更新时间：2023-01-14 02:40:07
STA Nanometer
Timing, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the timing closure is the major milestone which dictates when a chip can be released to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs.
【文件预览】：
静态时序分析详解.pdf