文件名称：数字秒表的设计
文件大小：36KB
文件格式：DOC
更新时间：2016-04-22 09:09:26
vhdl
十进制计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count10 is port(clr,start,clk: in bit; cout: out bit; library ieee; daout: out std_logic_vector(3 downto 0)); end count10; architecture a of count10 is signal temp:std_logic_vector(3 downto 0); begin process(clk,clr) begin if clr='1' then temp<="0000"; cout<='0'; elsif (clk'event and clk='1') then if start='1' then if temp>="1001" then temp<="0000"; cout<='1'; else temp<=temp+1; cout<='0'; end if; end if; end if; daout<=temp; end process; end a; 3.1.2六进制计数器（count6） 1.VHDL源程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count6 is port(clr,start,clk: in bit; daout: out std_logic_vector(3 downto 0); cout: out std_logic); end count6; architecture a of count6 is signal temp:std_logic_vector(3 downto 0); begin process(clk,clr) begin if clr='1' then temp<="0000"; cout<='0'; elsif (clk'event and clk='1') then if start='1' then if temp>="0101" then temp<="0000"; cout<='1'; else temp<=temp+1; cout<='0'; end if; end if; end if; end process; daout<=temp; end a; . 3. 2.数据选择模块 1.VHDL源程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity seltime is port( clr,clk: in bit; dain0,dain1,dain2,dain3,dain4,dain5 : in std_logic_vector( 3 downto 0); sel:out std_logic_vector( 2 downto 0); dout:out std_logic_vector( 3 downto 0)); end seltime; architecture a of seltime is signal temp:integer range 0 to 5; begin process(clk) begin if(clr='1') then dout<="0000"; sel<="000"; temp<=0; elsif(clk' event and clk='1') then if temp=5 then temp<=0; else temp<=temp+1; end if; case temp is when 0=>sel<="000";dout<=dain0; when 1=>sel<="001";dout<=dain1; when 2=>sel<="010";dout<=dain2; when 3=>sel<="011";dout<=dain3; when 4=>sel<="100";dout<=dain4; when 5=>sel<="101";dout<=dain5; end case; end if; end process; end a; 3.3.译码器模块 1.VHDL源程序 Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity deled is port(num: in std_logic_vector( 3 downto 0); led:out std_logic_vector(6 downto 0)); end deled; architecture a of deled is begin process(num) begin case num is when"0000"=>led<="1111110"; when "0001"=>led<="0110000"; when N"0010"=>led<="1101101"; when "0011"=>led<="1111001"; when N"0100"=>led<="0110011"; when "0101"=>led<="1011011"; when "0110"=>led<="1011111"; when "0111"=>led<="1110000"; when "1000"=>led<="1111111"; when "1001"=>led<="1111011"; when OTHERS=>led<="0000000"; end case; end process; end a; 3.4.蜂鸣报警模块 1.VHDL源程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alarm is port(clk, I:in std_logic; q:out std_logic); end alarm; architecture a of alarm is signal n:integer range 0 to 20; signal q0 :std_logic; begin process(clk) begin if(clk='1'and clk'event) then if i='0' then q0<='0'; n<=0; elsif (n<=19 and i='1') then q0<=not q0; n<=n+1; else q0<='0'; end if; end if; end process; q<=q0; end a; 3.5.总程序 在这个模块中，数据选择器是选择百分之一秒、十分之一秒、秒、十秒、分、十分的输出。 1.VHDL源程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity miaobiao is port( stop,start,clk,clk1:in std_logic; led: out std_logic_vector(6 downto 0); sel:out std_logic_vector(6 2ownto 0); q: out std_logic); end miaobiao; architecture a of miaobiao is component count10 port(clk,clr,start:in std_logic; count:out std_logic; daout:out std_logic_vector(3 downto 0)); end component; component seltime port( clk,clr: in std_logic; dain1,dain2,dain3,dain4,dain5,dain6:in std_logic_vector(3 downto 0); daout: out std_logic_vector(3 downto 0); sel: out std_logic_vector(2 downto 0) ); end component; component deled port( num: in std_logic_vector(3 downto 0); led: out std_logic_vector(6 downto 0) ); end component; component alarm port( clk,i:in std_logic; q:out std_logic ); end component; component count6 port( clk,clr,start:in std_logic; count:out std_logic; daout:ou std_logic_vector(3 downto 0) ); end component; signal s100,s10,s ,ts,m,tm: std_logic_vector(3 downto 0); signal cout: std_logic_vector(5downto 0); signal sdout: std_logic_vector(3 downto 0); begin count1:count10 port map(clk=>clk, clr=>stop, start=>start, cout=>cout(0),s100); count2: count10 port map (clk=>cout(0),stop,start,cout(1),s10); count3: count10 port map (cout(1),stop,start,cout(2),s); count4: count6 port map (cout(2), stop, start, cout (3),ts); count5: count10 port map (cout (3), stop, start, cout (4),m); count6: count6 port map (cout (4), stop, start, cout (5),tm); u0:seltime port map (clk1,stop,s100,s10,s,ts,m,tm,sdout,sel); u1:deled port map (sdout,led); u2:alarm port map (clk, cout (5),q); end a;