一种异步fifo实现(论文+hdl实现)

时间:2016-02-02 06:45:16
【文件属性】:

文件名称:一种异步fifo实现(论文+hdl实现)

文件大小:164KB

文件格式:RAR

更新时间:2016-02-02 06:45:16

异步fifo fifo

FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design techniques. There are many ways to design a FIFO wrong. There are many ways to design a FIFO right but still make it difficult to properly synthesize and analyze the design. This paper will detail one method that is used to design, synthesize and analyze a safe FIFO between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #1) is included.


【文件预览】:
wave.bmp
vsim.wlf
Asynchronous FIFO_201212181408840.pdf
tb.do
work
----fifomem()
--------_primary.dbs(601B)
--------verilog.psm(10KB)
--------verilog.prw(306B)
--------_primary.vhd(695B)
--------_primary.dat(490B)
----sync_w2r()
--------_primary.dbs(341B)
--------verilog.psm(6KB)
--------verilog.prw(251B)
--------_primary.vhd(449B)
--------_primary.dat(362B)
----wptr_full()
--------_primary.dbs(1KB)
--------verilog.psm(14KB)
--------verilog.prw(671B)
--------_primary.vhd(587B)
--------_primary.dat(751B)
----sync_r2w()
--------_primary.dbs(341B)
--------verilog.psm(6KB)
--------verilog.prw(251B)
--------_primary.vhd(449B)
--------_primary.dat(362B)
----fifo1()
--------_primary.dbs(1KB)
--------verilog.psm(11KB)
--------verilog.prw(79B)
--------_primary.vhd(800B)
--------_primary.dat(1KB)
----_info(2KB)
----rptr_empty()
--------_primary.dbs(968B)
--------verilog.psm(11KB)
--------verilog.prw(583B)
--------_primary.vhd(589B)
--------_primary.dat(680B)
----_temp()
----fifo1_tb()
--------_primary.dbs(2KB)
--------verilog.psm(15KB)
--------verilog.prw(1KB)
--------_primary.vhd(346B)
--------_primary.dat(878B)
----_vmake(26B)
src
----sync_w2r.v(345B)
----fifo1.v(2KB)
----fifo1_tb.v(924B)
----rptr_empty.v(1KB)
----wptr_full.v(1KB)
----fifomem.v(671B)
----sync_r2w.v(349B)
wave.do
fifo1.xml

网友评论

  • 不对啊 中间有一段读空了 还在读 21129ns时刻