文件名称：Writing testbenches using SystemVerilog.pdf
文件大小：1.77MB
文件格式：PDF
更新时间：2023-03-24 23:08:49
电子工程
Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing