A Design Methodology for Highly-Integrated Low-Power Receivers for Wireless Communications

【文件属性】：
文件名称：A Design Methodology for Highly-Integrated Low-Power Receivers for Wireless Communications
文件大小：6.29MB
文件格式：PDF
更新时间：2013-08-10 14:54:41
wireless communication Due to its potential to offer ubiquitous information access, wireless connectivity is playing an increasingly significant role in communications systems. The success of future wireless systems will depend heavily on their ability to provide high capacity while maintaining low cost, small form factor, and low power consumption in the portable devices. However, many existing commercial transceivers are expensive, consist of a large number of discrete components, and exhibit moderate to high levels of power consumption. One possible explanation for these inefficient solutions lies in the historically unilateral relationship between system designers and hardware designers. An efficient solution requires a design strategy which tightly incorporates implementation issues throughout the process of defining the system specifications. This thesis describes a design methodology which facilitates the evaluation of tradeoffs between implementation issues and overall system performance, focusing primarily on the receiver as an example. First, system-level specifications, such as modulation scheme and signal bandwidth, strongly influence the choice of receiver architecture, which in turn, has ramifications on the achievable power consumption and integration level. When system-level specifications are determined without considering their impact on receiver architecture selection, single-chip solutions may be very difficult to achieve or just simply infeasible.