V6 fpga LVDS传输

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文件名称：V6 fpga LVDS传输
文件大小：1.3MB
文件格式：PDF
更新时间：2015-05-25 17:35:04
Virtex-6 LVDS The Virtex®-6 FPGA SelectIO™ technology can perform 4X asynchronous oversampling at 1.25 Gb/s. The oversampling is accomplished using the ISERDESE1 primitive through the mixed-mode clock manager (MMCM) dedicated performance path. The ISERDESE1 is located in the SelectIO logic block and contains four phases of dedicated flip-flops used for sampling. The MMCM is an advanced PLL that has the capability to provide a phase-shifted clock on a low-jitter performance path.