文件名称：[图书]Digital VLSI Design with Verilog
文件大小：12.73MB
文件格式：PDF
更新时间：2013-05-10 07:17:06
VLSI Verilog ASIC 图书 book
来自硅谷技术学院的教科书。不同于以往传授verilog语法的书籍，这本书则通过配合实例，可以一步步学习并使用Verilog设计真正的VLSI，考虑Verilog用于VLSI设计中的多个方面，包括可综合性，仿真，芯片的可测设计以及工具的使用等等。 学习内容按周排列（12周，每周2节课）。 涉及的内容包括： Topic List (partial): Discussion: Modules and hierarchy; Blocking/nonblocking assignment; Combinational logic; Sequential logic; Behavioral modelling; RTL modelling; Gate-level modelling; Hardware timing and delays; Verilog parameters; Basic system tasks; Timing checks; Generate statement; Simulation event scheduling; Race conditions; Synthesizer operation; Synthesizable constructs; Netlist optimization; Synthesis control directives; Verilog influence on optimization; Use of SDF files; Test structures; Error correction basics. 实例包括： Lab Projects: Shift and scan registers; counters; memory and FIFO models; digital phase-locked loop (PLL); serial-parallel (and υ-υ) converter; serializer-deserializer (serdes); primitive gates; switch-level design; netlist back-annotation. 涉及的工具：VCS, Design Compiler, or QuestaSim