文件名称：Digital VLSI Systems Design.pdf
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VLSI
Chapter 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Chapter 2 2.2 2.4 2.5 2.6 2.7 2.8 xiii as an Example.………………………………... … The Karnaugh MAP Method of Optimization 1.5.1 FPGA Based Design: Video Compression Introduction to Digital VLSI Systems Design……… Twos Complement Addition/Subtraction………….….. 3 Evolution of VLSI Systems…………………………… 4 Applications of VLSI Systems………………………… 5 Processor Based Systems…………..………………….. 7 Embedded Systems……………………………………. 8 FPGA Based Systems.………………………………… 9 9 Digital System Design Using FPGAs…...………….…. 13 1.6.1 Spartan-3 FPGAs………………………………… 14 Scope of the Book……………………………….…….. 25 1.8.1 Approach……………….…………….………….. 25 Reconfigurable Systems Using FPGAs.....……………. 24 2.1 Numbering Systems…………………………………… 33 35 2.3 Codes……...…………..…..…………………………… 37 2.3.1 Binary and BCD Codes...………..….…………… 37 2.3.2 Gray Code……………………..………………… 39 2.3.3 ASCII Code…..…………………..……………… 40 2.3.4 Error Detection Code……………………............. 41 Boolean Algebra………………………………….……. 43 Boolean Functions Using Minterms and Maxterms....… 44 Logic Gates……………………………………………. 46 of Logic Circuits…………………………………….… 47 Combination Circuits………………………………….. 50 2.8.1 Multiplexers…………….……………………….. 50 2.8.2 Demultiplexers…………………………………... 51 Review of Digital Systems Design…………..……….. 33 vi Contents 2.9 2.10 2.11 2.12 2.14 Setup, Hold, and Propagation Delay Times 2.15 2.16 2.17 Chapter 3 Design of Combinational and Sequential Circuits 3.1 3.2 2.14.1 Estimation of Maximum Clock Frequency 2.15.3 Controlled Three-bit Binary Counter Using 2.15.2 Design of a Three-bit Counter Using 3.2.2 Realization of Majority Logic 3.2.8 A Design Example Using an Adder 2.8.3 Decoders…………………………………….…... 52 2.8.4 Magnitude Comparator………………………….. 53 2.8.5 Adder/Subtractor Circuits……………………….. 55 2.8.6 SSI and MSI Components……………………….. 58 Arithmetic Logic Unit…………………………………. 58 Programmable Logic Devices….……...………………. 59 2.10.1 Read-Only Memory……………………………. 61 2.10.2 Programmable Logic Array (PLA)....………….. 62 2.10.3 Programmable Array Logic (PAL)…………….. 63 Sequential Circuits…………………………………….. 64 Random Access Memory (RAM) …………………….. 72 2.13 Clock Parameters and Skew………………………….... 73 in a Register………………………………………….… 74 for a Sequential Circuit…………….…………... 75 2.14.2 Metastability of Flip-flops…………….……….. 76 Digital System Design Using SSI/MSI Components...... 77 2.15.1 Two-bit Binary Counter Using JK Flip-flops...… 77 T and D Flip-flops…………………………...…. 80 ROM and Registers….…………………………. 83 Algorithmic State Machine…………….……………… 85 Digital System Design Using ASM Chart and PAL.….. 87 2.17.1 Single Pulser Using ASM Chart………..………. 87 2.17.2 Design of a Vending Machine Using PAL…….. 90 Using Verilog………………………….….…………. 107 Introduction to Hardware Design Language…………. 107 Design of Combinational Circuits…….……………… 109 3.2.1 Realization of Basic Gates………….………….. 110 and Concatenation…...…………………………. 111 3.2.3 Shift Operations……….………………………... 112 3.2.4 Realization of Multiplexers……………….……. 113 3.2.5 Realization of a Demultiplexer…….…………… 116 3.2.6 Verilog Modeling of a Full Adder……………… 118 3.2.7 Realization of a Magnitude Comparator……….. 120 and a Magnitude Comparator.………………...... 121 Contents vii 3.3 3.4 Chapter 4 4.1 4.2 4.3 Chapter 5 5.1 Separation of Combinational and Sequential 5.2 5.3 5.4 5.5 5.6 5.7 Chapter 6 6.1 6.2 6.3 Chapter 7 7.1 Verilog Modeling of Sequential Circuits…………….. 123 3.3.1 Realization of a D Flip-flop…………………….. 123 3.3.2 Realization of Registers…………….…………... 124 3.3.3 Realization of a Counter………………….…….. 127 3.3.4 Realization of a Non-retriggerable Monoshot….. 128 3.3.5 Verilog Coding of a Shift Register…….……….. 130 3.3.6 Realization of a Parallel to Serial Converter….…132 3.3.7 Realization of a Model State Machine…………. 134 3.3.8 Pattern Sequence Detector………………….…... 137 Coding Organization……………………………...….. 139 3.4.1 Combinational Circuit Design………………...... 141 3.4.2 Sequential Circuit Design………………….….... 147 Writing a Test Bench for the Design………………. 165 Modeling a Test Bench………………….……………. 165 Test Bench for Combinational Circuits…….………… 169 Test Bench for Sequential Circuits….……………….. 174 RTL Coding Guidelines…………………………….. 187 Circuits……………………………………………….. 187 Synchronous Logic…………………………………… 187 Synchronous Flip-flop………………………………... 189 Realization of Time Delays…………………………... 190 Elimination of Glitches Using Synchronous Circuits... 193 Hold Time Violation in Asynchronous Circuits……... 194 RTL Coding Style……………………………………. 195 Simulation of Designs – Modelsim Tool…………… 217 VLSI Design Flow…………………………………… 217 Design Methodology………….……………………… 222 Simulation Using Modelsim………………………….. 225 6.3.1 Simulation Results of Combinational Circuits…. 230 6.3.2 Simulation Results of Sequential Circuits…….... 234 Synthesis of Designs – Synplify Tool………………. 255 Synthesis……………...…………………………...….. 255 7.1.1 Features of Synthesis Tool……………………… 255 6.3.3 Modelsim Command Summary………………... 246 viii Contents 7.3 Viewing Verilog Code as RTL Schematic Circuit 7.4 Optimization Effected in Synopsys Full and Parallel 7.5 7.6 Fixing Compilation Errors in Modelsim and Synplify 7.7 Chapter 8 8.1 8.2 8.3 Chapter 9 9.1 9.1.3 Simulation Results of Dual Address ROM 9.1.4 Synthesis Results for Dual Address ROM 9.1.5 Xilinx P&R Results for Dual Address ROM 9.2 9.2.1 Verilog Code for Single Address ROM Place and Route and Back Annotation Using Xilinx 9.2.3 Simulation Results of Single Address ROM 9.2.4 Synthesis Results for Single Address ROM 9.2.5 Xilinx P&R Results for Single Address ROM Performance Comparison of FPGAs of Two Vendors Place and Route ........ 7.2 Analysis of Design Examples Using Synplify Tool...... 256 Diagrams……………………………………………... 260 Cases…………………………………………………. 274 for a Design…………………………………………... 278 Tools…………………………………………………. 280 Synplify Command Summary……………………….. 283 ......…………………..……….. 295 Xilinx Place and Route ......................................……... 295 Xilinx Place and Route Tool Command Summary.…… 300 Project Navigator………………………….………….. 301 Design of Memories………….……………………… 319 On-chip Dual Address ROM Design………………… 319 9.1.1 Verilog Code for Dual Address ROM Design..... 320 9.1.2 Test Bench for Dual Address ROM Design……. 323 Design………………………………………….. 325 Design……..................................................…… 327 Design…………………………………...……... 328 Single Address ROM Design………………………… 329 Design……………………………………...…... 329 9.2.2 Test Bench for Single Address ROM Design….. 331 Design………………………………………...... 332 Design………………………………………..… 334 Design………………………………………..… 335 Contents ix 9.3 9.4 9.4.2 Verilog Code for External RAM Controller 9.4.3 Test Bench for External RAM Controller 9.4.4 Simulation Results for External RAM Controller 9.4.6 Xilinx P&R Results for the External RAM Chapter 10 10.1 10.2 10.3 Chapter 11 Development of Algorithms and Verification 11.1 9.4.1 Design of an External RAM Controller 11.1.1 Algorithm for Parallel Matrix Multiplication 11.1.2 Verification of DCTQ –I QIDCT Processes with 9.4.5 Synthesis Results for External RAM Controller On-Chip Dual RAM Design………………………….. 335 9.3.1 Verilog Code for Dual RAM Design…………… 337 9.3.2 Test Bench for the Dual RAM Design………..... 342 9.3.3 Simulation Results of Dual RAM Design……… 345 9.3.4 Synthesis Results for the Dual RAM Design…... 348 9.3.5 Xilinx P&R Results for the Dual RAM Design... 350 External Memory Controller Design………………..... 351 for Video Scalar Application………………….... 351 Design………………………………………...... 352 Design………………………………………..… 357 Design………………………………………….. 359 Design………………………………………….. 362 Controller Design……………...……………….. 364 Arithmetic Circuit Designs…………………………. 371 Digital Pipelining…………………………………….. 371 Partitioning of a Design…………………………......... 374 10.2.1 Partition of Data Width……………………….. 374 10.2.2 Partition of Functionality……………………... 374 Signed Adder Design………………………………… 375 10.3.1 Signed Serial Adder…………………………... 375 10.3.2 Parallel Signed Adder Design………………… 381 10.4 Multiplier Design…………………………………….. 395 10.4.1 Verilog Code for Multiplier Design…………... 398 Using High Level Languages……………………….. 417 2D-Discrete Cosine Transform and Quantization….... 418 for DCTQ.…………………………………….. 419 Fixed Pruning Level Control Using Matlab….. 421 x Contents 11.2 Automatic Quality Control Scheme for Image 11.2.1 Algorithm for Assessing Image Quality Automatic Pruning Level Control Incorporated 11.3 11.3.3 Assessment of Direction of Motion of Image 11.3.5 Results and Discussions of FOSS Motion Chapter 12 12.1 12.2 Architecture of a Video Encoder Using Automatic 12.3 Architecture for the FOSS Motion Estimation Chapter 13 13.1 13.1.3 Test Bench for the Functional Testing 11.2.3 Results and Discussions for the Fixed Architecture of Discrete Cosine Transform 13.1.6 Xilinx Place and Route Results for PCI 11.2.2 Verification of DCTQ –I QIDCT Processes with 11.3.2 The Fast One-at-a-time Step Search 11.3.4 Detection of Scene Change .....……………...… Fast Motion Estimation Algorithm for Real-Time Compression……………………………………...….. 431 Dynamically…………………………………... 433 Using Matlab………….………………………. 435 and Automatic Pruning Level Controls……..… 447 Video Compression…………………….…………….. 452 11.3.1 Introduction………………………….………... 452 Algorithm……………………………………... 454 Blocks…………………………………….…… 459 459 Estimation Algorithm………………………..... 461 Architectural Design………………………….…….. 4 73 and Quantization Processor…………..……………… 473 Quality Control Scheme and DCTQ Processor…….… 477 12.2.1 The Automatic Quality Controller……….…… 477 Processor…………………………………………...… 479 Project Design……………….………………………. 487 PCI Bus Arbiter…………………………………….... 487 13.1.1 Design of PCI Arbiter………………………… 490 13.1.2 Verilog Code for PCI Arbiter Design………… 492 of PCI Arbiter………………………………..... 496 13.1.4 Simulation Results……………………………. 498 13.1.5 Synthesis Results for PCI Arbiter…………….. 500 Arbiter………………………………………… 502 Contents xi 13.2 13.2.9 Verification of Verilog DCTQ –I QIDCT 13.2.11 Implementation of DCTQ/IQIDCT IP Chapter 14 Hardware Implementations Using FPGA 14.1 14.2 14.3 14.3.1 Verilog Code to Solve the Malfunctioning of 14.4 14.4.1 Verilog RTL Code for Traffic Light 14.5 13.2.2 Sequence of Operations of the Host 14.5.3 Hardware Requirements for the Real Time 14.5.4 Detailed Specification of the Real Time 13.2.8 Matlab Codes for Pre-processing Design of the DCTQ Processor…………….………… 502 13.2.1 Specification of DCTQ Processor…….……... 503 and the DCTQ Processors…………….…....… 504 13.2.3 Verilog Code for the DCTQ Design……….… 506 13.2.4 Test Bench for the DCTQ Design……….…… 526 13.2.5 Simulation Results for DCTQ Design……….. 531 13.2.6 Synthesis Results for DCTQ Design………..... 536 13.2.7 Place and Route Results for DCTQ Design….. 537 and Post-processing an Image.………….....… 538 Cores………………………………………… 544 13.2.10 Simulation Results…………………………... 545 Cores…………………………………………. 547 13.2.12 Capabilities of the IP Cores……………….…. 548 and I/O Boards……………………………………..... 555 FPGA Board Features………………………………... 556 Features of Digital Input/Output Board……………… 558 Problem on Some FPGA Boards and Its Solution….... 560 System Using XC4000 Series FPGA Boards..... 561 Traffic Light Controller Design……………………… 562 Controller………………………………..…… 565 14.4.2 Test Bench for the Traffic Light Controller…... 582 14.4.3 Simulation of Traffic Light Controller……….. 584 14.4.4 Synthesis Results of Traffic Light Controller… 586 14.4.5 Place and Route Results of Traffic Controller... 587 14.4.6 Hardware Setup of Traffic Light Controller….. 589 Real Time Clock Design……………………………... 592 14.5.1 Applications…………………………………... 592 14.5.2 Features……………………………………….. 593 Clock………………………………………….. 594 Clock………………………………...………... 597 xii Contents 14.5.5 14.5.6 14.5.7 14.5.8 14.5.9 Chapter 15 Projects Suggested for FPGA/ASIC 15.1 15.1.1 15.1.2 15.1.3 15.1.4 15.1.5 15.1.6 15.1.7 15.1.8 15.1.9 15.2 15.3 Issues Involved in the Design of Digital VLSI 15.4 15.4.1 Electrostatic Precipitator Controller – Detailed Specifications and Basic Architectures for a Couple of Applications Suggested for FPGA/ASIC Index...………………………………………………………………… 15.4.2 Architecture of JPEG/H.263/MPEG 1/ References..…………………………………………………………… Simplified Architecture of RTC.…………….. 599 Verilog Code for Real Time Clock…..……… 600 Test Bench for Real Time Clock Design..….... 640 Simulation Results of Real Time Clock...…… 643 Synthesis Results of Real Time Clock…..…... 645 14.5.10 Xilinx P&R Results………………..…….…... 646 14.5.11 Hardware Setup of Real Time Clock………... 648 Implementations……………………………….....… 659 Projects for Implementation………………………….. 659 Automotive Electronics……………………… 660 Avionics……………………………………... 661 Cameras…………………………………….... 662 Communication Systems…………………….. 662 Computers and Peripherals…………………... 663 Control Systems………………………..……. 663 Image/Video Processing Systems………..….. 664 Measuring Instruments…………………..…... 665 Medical Applications……………………..…. 666 15.1.10 Miscellaneous Applications…………………. 667 15.1.11 Music………………………………………… 669 15.1.12 Office Equipments…………………………… 670 15.1.13 Phones……………………………………….. 670 15.1.14 Security Systems…………………………….. 670 15.1.15 Toys and Games……...…………………….... 671 Embedded Systems Design…………………………... 672 Systems……………………………………………..... 673 Implementations…………………………………….... 674 an Embedded System…………………………. 675 MPEG 2 Codec……………………………...... 682 697 703