文件名称：ofdm 交织编码的Verilog实现
文件大小：256KB
文件格式：ZIP
更新时间：2013-05-27 04:08:52
交织 Verilog
ofdm发射机设计与实现的一个部分。 用ise仿真~~需自己写text文件~ 程序中有检测时会有两个错误，第一个是字符不匹配 自己用英文输入写一遍就行，第二个是少了一个begin~
【文件预览】：
rcount_1.vho
dint_ram2.sym
dint_ram.vhd
count24.edn
data_interleaver.ise_ISE_Backup
count24.veo
rcount_1.v
dint_ram2.v
dint_ram.edn
rcount_1.xco
_xmsgs
count24.asy
data_interleaver_xdb
----tmp()
dint_ram.xco
data_interleaver.v
dint_ram2.veo
data_interleaver.ise
dint_ram2.xco
count24.sym
rcount_1.veo
dint_ram2.mif
dint_ram2.edn
rcount_1.asy
dint_ram.veo
dint_ram.v
count24.v
dint_ram.asy
rcount_1.edn
data_interleaver.restore
rcount_1.vhd
dint_ram2.vhd
dint_ram2.vho
count24.vho
count24.xco
templates
----coregen.xml(5KB)
count24.vhd
rcount_1.sym
data_interleaver_summary.html
dint_ram2.asy
dint_ram.vho
dint_ram.sym