文件名称：AMBA AXI protocal
文件大小：2.54MB
文件格式：ZIP
更新时间：2015-09-28 07:41:13
AMBA AXI3
The AMBA AXI protocol supports high-performance, high-frequency system designs. The AXI protocol: • is suitable for high-bandwidth and low-latency designs • provides high-frequency operation without using complex bridges • meets the interface requirements of a wide range of components • is suitable for memory controllers with high initial access latency • provides flexibility in the implementation of interconnect architectures • is backward-compatible with existing AHB and APB interfaces. The key features of the AXI protocol are: • separate address/control and data phases • support for unaligned data transfers, using byte strobes • uses burst-based transactions with only the start address issued • separate read and write data channels, that can provide low-cost Direct Memory Access (DMA) • support for issuing multiple outstanding addresses • support for out-of-order transaction completion • permits easy addition of register stages to provide timing closure. The AXI protocol includes the optional extensions that cover signaling for low-power operation. The AXI protocol includes the AXI4-Lite specification, a subset of AXI4 for communication with simpler control register style interfaces within components. See Chapter B1 AMBA AXI4-Lite.
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