文件名称：跨时钟域设计.pdf
文件大小：564KB
文件格式：PDF
更新时间：2023-03-11 04:28:20
信号同步 IC设计
ic设计的一些夸时钟设计指导 Logic circuits having a single clock are the most elementary type of digital design. The reality is that modern digital designs are increasingly sophisticated; having multiple clocks driving different circuits and circuits that must reliably communicate with each other. Most data movement applications such as disk drive controllers, CDROM/DVD controllers, modems, network interfaces and network processors, have multiple clock domains and bear inherent challenges moving data across clock domains. In modern IC, ASIC and FPGA designs, the engineer has many software programs to help create million gate circuits, but these programs cannot solve the problem of signal synchronization. When signals travel from one clock domain to another, the signal appears to be asynchronous in the new clock domain. Since the engineer’s toolbox does not have the tools to handle this situation, it is up to the designer to know reliable design techniques that reduce the risk of failure for circuits communicating across clock domains. This paper explores the fundamentals of signal synchronization and demonstrates circuits a designer can use to handle signals that cross clock domains. It examines design methodologies for synchronizing single signals and ways of handling groups of signals including data busses thatcross clock domains