ASIC Design Flow Tutorial

【文件属性】：
文件名称：ASIC Design Flow Tutorial
文件大小：5.03MB
文件格式：PDF
更新时间：2016-05-16 01:26:53
asic design To design a chip,one needs to come up with the Specifications first, The next step is in the flow is to come up with the Structural and Functional Description.Once Functional Verification is completed, the RTL is converted into an optimized Gate Level Netlist. This step is called Logic/RTL synthesis.The next step in the ASIC flow is the Physical Implementation of the Gate Level Netlist.