文件名称:Top Down Digital VLSI Design From Architectures .pdf
文件大小:21.07MB
文件格式:PDF
更新时间:2022-07-01 13:00:13
VLSI FPGA Verilog
从架构到门级电路的自顶向下数字VLSI设计,Top-Down Digital VLSI Design From Architectures to Gate-Level Circuits and FPGAs
文件名称:Top Down Digital VLSI Design From Architectures .pdf
文件大小:21.07MB
文件格式:PDF
更新时间:2022-07-01 13:00:13
VLSI FPGA Verilog
从架构到门级电路的自顶向下数字VLSI设计,Top-Down Digital VLSI Design From Architectures to Gate-Level Circuits and FPGAs