文件名称：sdram sdram sdram
文件大小：1.23MB
文件格式：PDF
更新时间：2021-08-03 08:04:41
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle) - 15.6m s refresh interval