文件名称：COEN122:计算机架构
文件大小：2.17MB
文件格式：ZIP
更新时间：2024-04-21 02:29:37
COEN 122 计算机体系结构课程（Verilog） 实验1：4：1多路复用器实验2：算术逻辑单元实验3：寄存器文件，数据存储器和指令存储器实验4：管道缓冲区最终项目：流水线CPU的结构模型
【文件预览】：
COEN122-master
----Lab4()
--------assignment4_buffers.pdf(171KB)
--------EXWB.txt(2KB)
--------test.txt(1KB)
--------Lab4_waveform.PNG(13KB)
--------IFID.txt(901B)
--------IDEX.txt(2KB)
----Lab2()
--------Lab2_Waveform.PNG(19KB)
--------assignment2_alu.pdf(105KB)
--------ALU.txt(1KB)
--------ALU_test.txt(1KB)
----Lab1()
--------lab1_waveform.PNG(26KB)
--------mux.txt(783B)
--------assignment1_mux.pdf(103KB)
--------mux_test.txt(815B)
----Lab3()
--------register.txt(1KB)
--------assignment3_mem.pdf(104KB)
--------data.txt(979B)
--------instruction.txt(895B)
--------test.txt(2KB)
--------Lab3_waveform.PNG(32KB)
----Final Project()
--------if_design.txt(824B)
--------alu.txt(1KB)
--------ex_design.txt(2KB)
--------final_waveform6.PNG(68KB)
--------instruction_memory.txt(3KB)
--------sign_extender.txt(830B)
--------final_waveform8.PNG(64KB)
--------final_waveform3.PNG(81KB)
--------data_memory.txt(914B)
--------program_counter.txt(797B)
--------final_waveform4.PNG(70KB)
--------mux.txt(962B)
--------final_waveform1.PNG(81KB)
--------final_waveform2.PNG(72KB)
--------test_bench.txt(4KB)
--------Project.pdf(199KB)
--------register_file.txt(977B)
--------WorkingDatapath_2019.pdf(53KB)
--------COEN 122 Report.pdf(1.76MB)
--------and_gate.txt(771B)
--------final_waveform5.PNG(77KB)
--------or_gate.txt(829B)
--------final_waveform7.PNG(66KB)
--------id_design.txt(2KB)
--------control_unit.txt(4KB)
----README.md(248B)