DVI encode and decode source code for FPGA

【文件属性】：
文件名称：DVI encode and decode source code for FPGA
文件大小：152KB
文件格式：RAR
更新时间：2012-07-19 03:36:30
DVI FPGA Verilog firmware DVI 1.0 encode and decode source code, write with verilog, with simulation project, synplify project and all soure code. They're have been running on xilinx spartan3A FPGA. Can be used in real project directly. Use 3 DCM and about 2000 slices. Also including version_list file. file_list: core\ vssver.scc chnlbond.v dcminit.v decode.v DRAM16XN.v dvi_decoder.v dvi_encoder.v dvi_ip.v encode.v patten_gen.v phsaligner.v resync_1024fifo.v serdes_4b_10to1_fifo.v sync_monitor.v tmds_1c_1to10.v watch_dog.v resync_part_new.vhd

【文件预览】：
dvi_encoder_decoder_for fpga
----model()
--------VGA_Param.h(489B)
--------patten_gen_with_btn.v(14KB)
--------CY7C1338G_FT.v(17KB)
--------swap_ctrl.v(1KB)
--------dvi_patten_gen.v(2KB)
--------vga2.vhd(3KB)
--------patten_sel.v(1KB)
--------vssver.scc(128B)
--------patten_gen.v(11KB)
--------mcu_stimulus.vhd(18KB)
--------VGA_Controller.v(4KB)
----rtl()
--------core_gen()
--------ctrl_main.ucf(10KB)
--------vsync_stu_led.v(910B)
--------clk_ctrl.v(5KB)
--------reset_gen.v(611B)
--------dvi_ip()
--------common()
--------new_resync()
--------ctrl_main.v(8KB)
--------up_registers.v(3KB)
--------dvi_ctrl.v(1KB)
--------trig_cnt.v(646B)
----version.txt(2KB)
----sim()
--------sim.td(216B)
--------dvi_demo.mpf(60KB)
--------glbl_set.h(20B)
--------sram_data.TXT(0B)
--------clean_project.bat(58B)
--------s3a_logo.v(36KB)
--------tb_dvi_demo.v(4KB)
--------reg_data.TXT(159B)
--------dvi_tx_fifo.mif(27KB)
--------glbl.v(1KB)
--------vssver.scc(192B)
--------gamma_data.TXT(0B)
--------restart(26B)
--------vlog.opt(6B)
----syn()
--------glbl_set.h(0B)
--------div_test.prj(6KB)