文件名称：vmm_tutorial_sv
文件大小：349KB
文件格式：PDF
更新时间：2015-09-21 08:19:39
sv vmm vcs
This tutorial is a beginner’s guide to using the VMM methodology, with the SystemVerilog language. You can simulate your testbenches with VCS. With using the VMM methodology, you can quickly build a layered testbench. These testbenches support high-level tests using constrained random stimulus and functional coverage to indicate which areas of the design you have checked.