文件名称：Open Host Controller Interface Specification
文件大小：670KB
文件格式：PDF
更新时间：2011-03-25 03:32:14
ohci openhci usb
TABLE OF CONTENTS
1. INTRODUCTION.........................................................................................................1
2. TERMS AND ABBREVIATIONS.................................................................................2
3. ARCHITECTURAL OVERVIEW..................................................................................6
3.1 Introduction..........................................................................................................6
3.2 Data Transfer Types............................................................................................7
3.3 Host Controller Interface.....................................................................................7
3.3.1 Communication Channels............................................................................................7
3.3.2 Data Structures...........................................................................................................8
3.4 Host Controller Driver Responsibilities...........................................................12
3.4.1 Host Controller Management....................................................................................12
3.4.2 Bandwidth Allocation................................................................................................12
3.4.3 List Management......................................................................................................13
3.4.4 Root Hub..................................................................................................................13
3.5 Host Controller Responsibilities......................................................................13
3.5.1 USB States...............................................................................................................13
3.5.2 Frame management...................................................................................................14
3.5.3 List Processing..........................................................................................................14
4. DATA STRUCTURES...............................................................................................15
4.1 Overview.............................................................................................................15
4.2 Endpoint Descriptor..........................................................................................16
4.2.1 Endpoint Descriptor Format......................................................................................16
4.2.2 Endpoint Descriptor Field Definitions........................................................................17
4.2.3 Endpoint Descriptor Description...............................................................................18
4.3 Transfer Descriptors.........................................................................................19
4.3.1 General Transfer Descriptor......................................................................................19
4.3.1.1 General Transfer Descriptor Format...................................................................20
4.3.1.2 General Transfer Descriptor Field Definitions.....................................................20
4.3.1.3 General Transfer Descriptor Description.............................................................21
4.3.1.3.1 Buffer Address Determination.....................................................................21
4.3.1.3.2 Packet Size..................................................................................................21
4.3.1.3.3 Condition Codes..........................................................................................22
4.3.1.3.4 Sequence Bits..............................................................................................22
4.3.1.3.5 Transfer Completion....................................................................................23
4.3.1.3.6 Transfer Errors............................................................................................23
4.3.1.3.6.1 Transmission Errors..............................................................................24
4.3.1.3.6.2 Sequence Errors...................................................................................24
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OpenHCI - Open Host Controller Interface Specification for USB
4.3.1.3.6.3 System Errors.......................................................................................25
4.3.1.3.7 Special Handling..........................................................................................25
4.3.1.3.7.1 NAK.....................................................................................................25
4.3.1.3.7.2 Stall......................................................................................................25
4.3.2 Isochronous Transfer Descriptor...............................................................................25
4.3.2.1 Isochronous Transfer Descriptor Format............................................................25
4.3.2.2 Isochronous Transfer Descriptor Field Definitions..............................................26
4.3.2.3 Isochronous Transfer Descriptor Description......................................................26
4.3.2.3.1 Buffer Addressing........................................................................................27
4.3.2.3.2 Data Packet Size.........................................................................................28
4.3.2.3.3 Status..........................................................................................................28
4.3.2.3.4 Transfer Completion....................................................................................28
4.3.2.3.5 Transfer Errors............................................................................................28
4.3.2.3.5.1 Transmission Errors..............................................................................29
4.3.2.3.5.2 Sequence Errors...................................................................................29
4.3.2.3.5.3 Time Errors..........................................................................................29
4.3.2.3.5.4 System Errors.......................................................................................30
4.3.2.3.6 Special Handling..........................................................................................31
4.3.2.3.6.1 NAK and STALL.................................................................................31
4.3.2.4 PacketStatusWord..............................................................................................31
4.3.2.4.1 Packet Status Word Field Definitions...........................................................31
4.3.3 Completion Codes.....................................................................................................32
4.3.3.1 Condition Code Description...............................................................................33
4.4 Host Controller Communications Area............................................................33
4.4.1 Host Controller Communications Area Format..........................................................34
4.4.2 Host Controller Communications Area Description...................................................34
4.4.2.1 HccaInterruptTable............................................................................................34
4.4.2.2 HccaFrameNumber............................................................................................35
4.4.2.3 HccaDoneHead..................................................................................................35
4.5 Endpoint List Processing.................................................................................36
4.6 Transfer Descriptor Queue Processing...........................................................37
5. HOST CONTROLLER DRIVER................................................................................38
5.1 Host Controller Management............................................................................38
5.1.1 Initialization..............................................................................................................38
5.1.1.1 Load and Locate................................................................................................39
5.1.1.2 Verify Host Controller and Allocate Resources...................................................39
5.1.1.3 Take Control of Host Controller.........................................................................40
5.1.1.3.1 SMM Driver, Power-Up..............................................................................40
5.1.1.3.2 BIOS Driver................................................................................................40
5.1.1.3.3 OS Driver, SMM Active..............................................................................41
5.1.1.3.4 OS Driver, BIOS Active..............................................................................41
5.1.1.3.5 OS Driver, neither SMM nor BIOS.............................................................41
5.1.1.3.6 SMM Driver, Re-Entry................................................................................42
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OpenHCI - Open Host Controller Interface Specification for USB
5.1.1.4 Setup Host Controller........................................................................................42
5.1.1.5 Begin Sending SOFs...........................................................................................42
5.1.2 Operational States.....................................................................................................43
5.1.2.1 USBRESET..........................................................................................................43
5.1.2.2 USBOPERATIONAL..............................................................................................43
5.1.2.3 USBSUSPEND......................................................................................................43
5.1.2.4 USBRESUME.......................................................................................................44
5.2 Schedule.............................................................................................................44
5.2.1 Sample Host Controller Driver Definitions................................................................46
5.2.2 Miscellaneous Definitions..........................................................................................46
5.2.3 Host Controller Descriptors Definitions.....................................................................47
5.2.4 Host Controller Driver Descriptor Definitions...........................................................48
5.2.5 Host Controller Endpoints........................................................................................50
5.2.6 Host Controller Driver Internal Definitions................................................................51
5.2.7 Endpoint Descriptor Lists.........................................................................................54
5.2.7.1 Bulk and Control................................................................................................54
5.2.7.1.1 Adding........................................................................................................54
5.2.7.1.2 Removing....................................................................................................56
5.2.7.1.3 Pause...........................................................................................................59
5.2.7.2 Interrupt.............................................................................................................61
5.2.7.2.1 Polling Rate.................................................................................................64
5.2.7.2.2 Adding........................................................................................................66
5.2.7.2.3 Removing....................................................................................................66
5.2.7.2.4 Pause...........................................................................................................67
5.2.7.3 Isochronous.......................................................................................................67
5.2.7.3.1 Adding........................................................................................................68
5.2.7.3.2 Removing....................................................................................................68
5.2.7.3.3 Pause...........................................................................................................68
5.2.8 Transfer Descriptor Queues......................................................................................68
5.2.8.1 The NULL or Empty Queue...............................................................................68
5.2.8.2 Adding to a Queue.............................................................................................69
5.2.8.3 Removing from a Queue.....................................................................................73
5.2.8.4 Cancel................................................................................................................74
5.2.9 Done Queue..............................................................................................................75
5.2.10 USB Bandwidth Allocation.....................................................................................78
5.2.10.1 Scheduling Overrun Errors...............................................................................78
5.2.11 ControlBulkServiceRatio........................................................................................79
5.3 Host Controller Interrupt...................................................................................80
5.4 FrameInterval Counter.......................................................................................85
5.5 Root Hub............................................................................................................86
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OpenHCI - Open Host Controller Interface Specification for USB
6. HOST CONTROLLER..............................................................................................87
6.1 Introduction........................................................................................................87
6.2 USB States.........................................................................................................87
6.2.1 UsbOperational.........................................................................................................88
6.2.2 UsbReset..................................................................................................................89
6.2.3 UsbSuspend..............................................................................................................89
6.2.4 UsbResume...............................................................................................................89
6.3 Frame Management...........................................................................................90
6.3.1 Frame Timing............................................................................................................90
6.3.2 StartOfFrame (SOF) Token Generation.....................................................................91
6.3.3 HccaFrameNumber Update.......................................................................................91
6.4 List Processing..................................................................................................92
6.4.1 Priority.....................................................................................................................92
6.4.1.1 List Priority........................................................................................................93
6.4.1.1.1 Periodic Lists...............................................................................................93
6.4.1.1.2 Nonperiodic Lists........................................................................................93
6.4.1.2 Endpoint Descriptor Priority..............................................................................94
6.4.1.3 Transfer Descriptor Priority................................................................................95
6.4.2 List Service Flow......................................................................................................95
6.4.2.1 List Enabled Check............................................................................................95
6.4.2.2 Locating Endpoint Descriptors...........................................................................97
6.4.3 Endpoint Descriptor Processing................................................................................98
6.4.4 Transfer Descriptor Processing.................................................................................99
6.4.4.1 Isochronous Relative Frame Number Calculation................................................99
6.4.4.2 Packet Address and Size Calculation..................................................................99
6.4.4.3 Packet Transfer Time Check.............................................................................101
6.4.4.4 Largest Data Packet Counter Operation...........................................................102
6.4.4.5 Status Writeback..............................................................................................102
6.4.4.5.1 General Transfer Descriptor Status Writeback...........................................102
6.4.4.5.2 Isochronous Transfer Descriptor Status Writeback....................................103
6.4.4.6 Transfer Descriptor Retirement........................................................................103
6.4.5 Done Queue............................................................................................................104
6.4.5.1 Done Queue Interrupt Counter.........................................................................104
6.5 Interrupt Processing........................................................................................105
6.5.1 SchedulingOverrun Event........................................................................................105
6.5.2 WritebackDoneHead Event.....................................................................................106
6.5.3 StartOfFrame Event................................................................................................106
6.5.4 ResumeDetected Event...........................................................................................106
6.5.5 UnrecoverableError Event......................................................................................106
6.5.6 FrameNumberOverflow Event.................................................................................106
6.5.7 RootHubStatusChange Event..................................................................................107
6.5.8 OwnershipChange Event.........................................................................................107
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OpenHCI - Open Host Controller Interface Specification for USB
6.6 Root Hub..........................................................................................................107
7. OPERATIONAL REGISTERS.................................................................................108
7.1 The Control and Status Partition....................................................................109
7.1.1 HcRevision Register................................................................................................109
7.1.2 HcControl Register.................................................................................................109
7.1.3 HcCommandStatus Register....................................................................................112
7.1.4 HcInterruptStatus Register......................................................................................113
7.1.5 HcInterruptEnable Register....................................................................................115
7.1.6 HcInterruptDisable Register...................................................................................116
7.2 Memory Pointer Partition................................................................................117
7.2.1 HcHCCA Register...................................................................................................117
7.2.2 HcPeriodCurrentED Register.................................................................................117
7.2.3 HcControlHeadED Register...................................................................................118
7.2.4 HcControlCurrentED Register................................................................................118
7.2.5 HcBulkHeadED Register........................................................................................119
7.2.6 HcBulkCurrentED Register.....................................................................................119
7.2.7 HcDoneHead Register............................................................................................120
7.3 Frame Counter Partition..................................................................................120
7.3.1 HcFmInterval Register............................................................................................120
7.3.2 HcFmRemaining Register.......................................................................................121
7.3.3 HcFmNumber Register...........................................................................................122
7.3.4 HcPeriodicStart Register........................................................................................122
7.3.5 HcLSThreshold Register.........................................................................................123
7.4 Root Hub Partition...........................................................................................123
7.4.1 HcRhDescriptorA Register......................................................................................124
7.4.2 HcRhDescriptorB Register......................................................................................125
7.4.3 HcRhStatus Register...............................................................................................126
7.4.4 HcRhPortStatus[1:NDP] Register...........................................................................128
APPENDIX A—PCI INTERFACE................................................................................132
PCI CONFIGURATION...............................................................................................132
PCI Configuration Spaces for OpenHCI-compliant USB Host Controller.........133
COMMAND Register.......................................................................................................134
CLASS_CODE Register...................................................................................................134
BAR_OHCI Register........................................................................................................135
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OpenHCI - Open Host Controller Interface Specification for USB
APPENDIX B—LEGACY SUPPORT INTERFACE SPECIFICATION........................136
OVERVIEW.................................................................................................................136
OPERATIONAL THEORY..........................................................................................137
Keyboard/Mouse Input..........................................................................................137
Keyboard Output...................................................................................................138
Emulation Interrupts..............................................................................................138
Mixed Environment.........................................................................................................139
Gate A20 Sequence.........................................................................................................139
SYSTEM REQUIREMENTS........................................................................................140
Host Controller Mapping.......................................................................................140
SMI Signaling.........................................................................................................141
Intercept Port 60h and 64h Accesses..................................................................141
Interrupts................................................................................................................141
Run-time Memory ..................................................................................................141
PROGRAMMING INTERFACE...................................................................................142
Modifications to existing registers......................................................................142
HcRevision Register........................................................................................................142
Legacy Support Registers....................................................................................142
HceInput Register............................................................................................................143
HceOutput Register.........................................................................................................143
HceStatus Register...........................................................................................................144
HceControl Register........................................................................................................145
IMPLEMENTATION NOTES.......................................................................................146
Emulation Interrupt Decode..................................................................................146
A20 Gate.................................................................................................................146