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文件名称：Stratix IV GX 开发套件参考手册
文件大小：1.87MB
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更新时间：2022-11-16 14:34:52
Stratix4 Altera FPGA 开发套件 Reference
This document describes the hardware features of the Stratix®
IV GX FPGA
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
The Stratix IV GX FPGA development board provides a hardware platform for
developing and prototyping low-power, high-performance, and logic-intensive
designs. The board provides a wide range of peripherals and memory interfaces to
facilitate the development of the Stratix IV GX FPGA designs.
Two High-Speed Mezzanine Card (HSMC) connectors are available to add additional
functionality via a variety of HSMC cards available from both Altera and various
partners
Design advancements and innovations, such as the 8.5 Gbps transceiver modules, the
PCI Express hard IP implementation, and programmable power technology ensure
that designs implemented in the Stratix IV GX FPGAs operate faster, with lower
power than in previous FPGA families.
The board features the following major component blocks:
■ EP4SGX230KF40 FPGA in the 1517-pin FineLine BGA Package
■ 228,000 LEs
■ 91,200 adaptive logic modules (ALMs)
■ 17,133 Kbit on-die memory
■ 126.5 Gbps transceivers (PMA only)
■ 2 PCI Express hard IP blocks
■ 8 phase locked loops (PLLs)
■ 1288 18x18 multipliers
■ 0.9-V core power
■ MAX®
II CPLD EPM2210 System Controller in the 256-pin FineLine BGA Package
■ 1.8-V core power
■ FPGA Configuration Circuitry
■ MAX®
II CPLD EPM2210 System Controller and Flash Fast Passive Parallel
(FPP) configuration
■ On-Board USB-BlasterTM
for use with the Quartus
®
II Programmer
■ On-Board Clocking Circuitry
■ 50-MHz/100-MHz/125-MHz/148.5-MHz/155.52-MHz/156.25-MHz oscillator
■ SMA connectors for external clock input
■ SMA connectors for clock output
■ Memory devices
■ 512-Mbyte DDR3 SDRAM with a 64-bit data bus (bottom port)
■ 128-Mbyte DDR3 SDRAM with a 16-bit data bus (top port)
■ Two 4-Mbyte QDRII+ SRAMs with 18-bit data buses
■ 2-Mbyte SSRAM with 36-bit data buses
■ 64-Mbyte synchronous flash
■ General User I/O
■ 16 user LEDs
■ Two-line character LCD display
■ One configuration done LED
■ One transmit/receive LED (TX/RX) per HSMC interface
■ Four PCI Express LEDs
■ Four Ethernet LEDs
■ Push-Button Switches
■ One user reset (CPU Reset)
■ One configuration reset
■ Three general user push-button switches
■ DIP Switches
■ Eight user DIP switches
■ Eight MAX
II control DIP switches
■ Power
■ 16-V – 20-V DC input
■ PCI Express edge connector power
■ On-Board power measurement circuitry
■ Mechanical
■ PCI Express half-length full-height (6.6” x 4.376”)
■ PCI Express chassis or bench-top operation