文件名称：IEEE Standard Test Access Port and Boundary-Scan Architecture
文件大小：1.27MB
文件格式：PDF
更新时间：2010-08-29 10:15:25
JTAG
This standard defines a test access port and boundary-scan architecture for digital integrated circuits and for
the digital portions of mixed analog/digital integrated circuits. The facilities defined by the standard seek to
provide a solution to the problem of testing assembled printed circuit boards and other products based on
highly complex digital integrated circuits and high-density surface-mounting assembly techniques. They
also provide a means of accessing and controlling design-for-test features built into the digital integrated circuits
themselves. Such features might, for example, include internal scan paths and self-test functions as
well as other features intended to support service applications in the assembled product.