文件名称:verilog RTL级代码编写指导(20篇精华文章)
文件大小:9.59MB
文件格式:RAR
更新时间:2014-12-29 16:07:31
verilog RTL
verilog RTL级代码编写指导(20篇精华文章)目录: Actel HDL Coding Style Guide; Advanced High-level HDL Design Techniques for Programmable Logic; Designing Safe Verilog State Machines with Synplify; fpga优秀设计的十条戒律; Guide to HDL Coding Styles for Synthesis; IEEE P1364.1_IEEE Standard for Verilog Register Transfer Level Synthesis; IEEE P1364.1D1.4_Draft Standard for Verilog RTL Synthesis; Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!; Practical FSM Analysis for Verilog; Re-timing for Performance Improvement in FPGA Designs; RTL Coding Styles That Yield Simulation and Synthesis Mismatches; State Machine Coding Styles for Synthesis; State machine design techniques for Verilog and VHDL; Synthesis and Simulation Design Guide; The Verilog Golden Reference Guide; Verilog Coding Style for Efficient Digital Design ; Verilog HDL Coding(Motorola); Verilog HDL Synthesis A Practical Primer; Xilinx:HDL Coding Style ; 可综合的Verilog语法(剑桥大学,影印)。