文件名称：High Performance Integer Arithmetic Circuit Design on FPGA Architecture.pdf
文件大小：5.43MB
文件格式：PDF
更新时间：2022-09-16 04:44:34
FPGA Architectur Integer Arithmet
In this book, we describe the optimized implementations of several arithmetic datapath, controlpath, and pseudorandom sequence generator circuits. We explore regular, modular, cascadable, and bit-sliced architectures for these circuits, by directly instantiating the target FPGA-specific primitives in the HDL specifications of the circuits. We justify every proposed architecture with detailed mathematical analyses. We improve performance by enforcing a constrained placement of the circuit building blocks, by placing the logically related hardware primitives in close proximity to one another, thereby minimizing the routing delay. This is accomplished by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File” (.ucf) format to the FPGA CAD tool.