【文件属性】:
文件名称:一位二进制全加/减器设计
文件大小:248KB
文件格式:RAR
更新时间:2011-12-28 02:56:58
原理图,vhdl
library ieee;
use ieee.std_logic_1164.all;
entity addt is
port (ain,bin,cin :in std_logic;
cout,sum :out std_logic);
end entity addt;
architecture fd1 of addt is
component h_adder
port(a,b: in std_logic;
co,so:out std_logic);
end component;
component or2a
port(a,b:in std_logic;
c:out std_logic);
end component;
signal d,e,f :std_logic;
begin
u1:h_adder port map(a=>ain,b=>bin,co=>d,so=>e);
u2:h_adder port map(a=>e,b=>cin,co=>f,so=>sum);
u3:or2a port map(a=>d,b=>f,c=>cout);
end architecture fd1;