转载请注明原地址：http://www.cnblogs.com/connorzx/p/3674178.html
调时电路正常工作。一切正常。发现做FPGA还是得从数电的思路思考，设置一个预置使能端，预置数一直都可以设置。
代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clock is
Port ( clk : in STD_LOGIC;
btn0: in STD_LOGIC;
btn1: in STD_LOGIC;
load: in STD_LOGIC;
led0: out STD_LOGIC;
seg : out STD_LOGIC_VECTOR ( downto );
seg7:out STD_LOGIC;
an : out STD_LOGIC_VECTOR ( downto ));
end clock; architecture Behavioral of clock is
signal num:STD_LOGIC_VECTOR ( downto );
signal hour_h:STD_LOGIC_VECTOR ( downto );
signal hour_l:STD_LOGIC_VECTOR ( downto );
signal min_h:STD_LOGIC_VECTOR ( downto );
signal min_l:STD_LOGIC_VECTOR ( downto );
signal second_h:STD_LOGIC_VECTOR ( downto );
signal second_l:STD_LOGIC_VECTOR ( downto );
signal hour_l_t:STD_LOGIC_VECTOR ( downto );
signal hour_h_t:STD_LOGIC_VECTOR ( downto );
signal min_l_t:STD_LOGIC_VECTOR ( downto );
signal min_h_t:STD_LOGIC_VECTOR ( downto );
signal an_sel:STD_LOGIC_VECTOR ( downto );
signal cnt: INTEGER;
signal cnt1: INTEGER;
signal cnt2: INTEGER;
signal cnt3: INTEGER;
signal sclk: STD_LOGIC;
signal aclk: STD_LOGIC;
signal shine:STD_LOGIC;
begin
led0<=shine;
process(clk)
begin
if(clk'event and clk='') then
if(cnt=) then
cnt<=;
sclk<=not sclk;
else
cnt<=cnt+;
end if;
end if;
end process; process(clk)
begin
if(clk'event and clk='') then
if(cnt2=) then
cnt2<=;
if(an_sel="") then
an_sel<="";
else
an_sel<=an_sel+'';
end if;
else
cnt2<=cnt2+;
end if;
end if;
end process; process(load,clk,btn0,btn1)
begin
if(load='')then
if(clk'event and clk='') then
if(btn0='') then
if(cnt1=) then
cnt1<=;
if(hour_h_t="" and hour_l_t="" ) then
hour_h_t<="";
hour_l_t<="";
elsif(hour_l_t="")then
hour_h_t<=hour_h_t+'';
hour_l_t<="";
else
hour_l_t<=hour_l_t+'';
end if;
else
cnt1<=cnt1+;
end if;
elsif(btn1='')then
if(cnt3=) then
cnt3<=;
if(min_h_t="" and min_l_t="" ) then
min_h_t<="";
min_l_t<="";
elsif(min_l_t="")then
min_h_t<=min_h_t+'';
min_l_t<="";
else
min_l_t<=min_l_t+'';
end if;
else
cnt3<=cnt3+;
end if;
end if;
end if;
end if;
end process; process(sclk,load)
begin
if(load='') then
min_l<=min_l_t;
min_h<=min_h_t;
hour_l<=hour_l_t;
hour_h<=hour_h_t;
else
if(sclk'event and sclk='') then
shine<=second_l();
if(second_h="" and second_l="") then
second_h<="";
second_l<="";
min_l<=min_l+'';
if(min_h="" and min_l="") then
min_h<="";
min_l<="";
hour_l<=hour_l+'';
if(hour_h="" and min_l="") then
hour_h<="";
hour_l<="";
elsif(hour_l="")then
hour_h<=hour_h+'';
hour_l<="";
end if;
elsif(min_l="") then
min_h<=min_h+'';
min_l<="";
end if;
elsif(second_l="") then
second_h<=second_h+'';
second_l<="";
else
second_l<=second_l+'';
end if;
end if;
end if;
end process; process(an_sel,second_l,second_h,min_l,min_h,hour_l,hour_h)
begin
case an_sel is
when ""=>an<="";num<=min_l;seg7<='';
when ""=>an<="";num<=min_h;seg7<='';
when ""=>an<="";num<=hour_l;seg7<='';
when ""=>an<="";num<=hour_h;seg7<='';
when others=>null;
end case;
case num is
when x""=>seg<=b"";
when x""=>seg<=b"";
when x""=>seg<=b"";
when x""=>seg<=b"";
when x""=>seg<=b"";
when x""=>seg<=b"";
when x""=>seg<=b"";
when x""=>seg<=b"";
when x""=>seg<=b"";
when x""=>seg<=b"";
when others=>null;
end case;
end process;
end Behavioral;
约束文件
NET "clk" LOC = "B8";
NET "led0" LOC ="M5";
NET "an<0>" LOC="K14";
NET "an<1>" LOC="M13";
NET "an<2>" LOC="J12";
NET "an<3>" LOC="F12";
NET "seg7" LOC="N13";
NET "seg<6>" LOC="L14";
NET "seg<5>" LOC="H12";
NET "seg<4>" LOC="N14";
NET "seg<3>" LOC="N11";
NET "seg<2>" LOC="P12";
NET "seg<1>" LOC="L13";
NET "seg<0>" LOC="M12";
NET "btn1" LOC = "M4";
NET "btn0" LOC = "A7";
NET "load" LOC="P11";